General-purpose scalar processors in general adopt a cache mechanism realized by hardware control. In cache control mechanism realized by hardware, data to be loaded from a memory by a processor or data to be stored in a memory is stored in a cache.
Since cache control intends to speed up memory access by holding data whose reusability is high in a cache memory, crucial is how data whose reusability is high is held in a cache.
A cache mechanism realized by hardware control in general adopts a control system of storing data whose reusability is high in a cache memory by using an LRU (Least Recently Used) system or the like.
In a cache control system using the LRU system or the like, however, data whose reusability is high will not be always held in a cache, so that use efficiency of a cache can not be increased satisfactorily.
For solving such a problem, several methods are proposed of storing data into a cache memory by software control, one example of which is disclosed in Patent Literature 1 or Patent Literature 2.
The cache memory system recited in Patent Literature 1 enables data whose reusability is high to be stored in a cache memory by controlling use of a cache memory based on a kind of access instruction to a main memory.
Cache control system realized by software enables only data whose reusability is high to be stored in a cache as compared with control by hardware using LRU or the like.
Patent Literature 1: Japanese Patent Laying-Open No. 6-202951.
The existing cache control systems realized by software which are proposed in Patent Literature 1 and the like have a problem that cache control can not be dynamically changed during program operation, so that cache use efficiency can not be increased satisfactorily.
The reason is that since the control system is cache control based on designation by an access instruction, data to be stored in a cache is determined at the time of compiling a program, so that cache storage control of data can not be dynamically controlled.